Row and/or column redundancy has been used to improve the yield of memory devices such as static random access memory (SRAM) devices. A fuse element is typically placed in series with each word line in a main memory array. When a memory cell is determined to be defective, the fuse for the corresponding word line is blown to de-couple the main address decoder from the row incorporating the defective memory cell. The address of the defective row is programmed into a spare address decoder that selects a spare row of memory cells in response to subsequent read or write access operations to the defective address in the main memory array.
Traditional row redundancy techniques, however, do not scale well for content addressable memory (CAM) devices. A CAM device is a binary or ternary storage device that can simultaneously compare a specific pattern of comparand data with data stored in each row of CAM cells in its CAM array. Match results are reflected on match lines that are provided to a priority encoder that translates the matched location into a match address or CAM index for output from the CAM device. Each row of CAM cells is typically connected to a word line as in conventional SPAMs and at least one match line. Thus, in order to use traditional row redundancy techniques in a CAM array, each row of CAM cells would use a first fuse for the word line and a second fuse for the match line. Additionally, to ensure that the de-coupled match line did not provide erroneous data to the priority encoder, an additional pull-down circuit would be needed for each match line to guarantee that the de-coupled match line indicated a mismatch state for the defective row of CAM cells. The additional fuse per row, and pull-down circuitry per row, would increase the size of the CAM array. As fuses typically do not scale well with process technologies, this increase in the number of fuses is not readily remedied by migration to a smaller geometry fabrication process. Thus, it would be desirable to provide a row redundancy scheme for CAMs that is more area efficient than using fuses on each word line and each match line.
In addition, since manufacturing defects may not be uniform across a wafer, defective cells may be concentrated in certain portions of a CAM device. Thus, in a CAM device having a number of CAM blocks each including a main CAM array and a spare or redundant row, the defective cells may be concentrated in one or more of the CAM blocks. Consequently, while first CAM blocks may be defect free, second CAM blocks may have more than one defective row. Since each CAM block has only one spare row and therefore can replace only one defective row, the second CAM blocks having more than one defective row may not be usable, even though spare rows may be available in other CAM blocks. Thus, it would also be desirable to provide a row redundancy scheme for CAMs that allow spare row(s) from a first CAM block to be used to replace a defective row in a second CAM block.